Technical / Research - Page 18

Spin Transfer Technologies (STT) and Singulus Technologies will collaborate to apply advanced deposition techniques to support commercial development of STT’s novel MRAM memory devices. The companies will use Singulus TIMARIS deposition tool to create magnetic layer stacks with STT’s design specifications. These layer stacks will then be processed at STT contracted facilities into memory arrays for testing, optimization, and eventually, pre-commercial prototyping.

Singulus has already sold several TIMARIS systems for MRAM companies (including Grandis and Crocus). STT is working towards Orthogonal Spin Transfer MRAM or OST-MRAM for short. Back in October 2008 we have interviewed Vincent Chun, the executive in charge at Spin Transfer Technologies.

Aeroflex Colorado Springs has licensed MRAM technology from Everspin for the development of HiRel nonvolatile memory solutions for aerospace and defense applications. Aeroflex will develop 4Mb and 16Mb MRAM monolithic solutions with guaranteed total ionizing dose and single event effect hardness. Aeroflex envisions HiRel MRAM solutions being used with microprocessors, DSP engines, storage systems, instruments, and reconfigurable FPGAs that require guaranteed total ionizing dose and single event hardness.

Aeroflex’s MRAM roadmap includes a family of -55oC to +125oC, QML products offered in ceramic packages per a Standard Microcircuit Drawing (SMD). As a replacement for 3.3 volt asynchronous SRAM, Aeroflex products will be 8-bit parallel I/O solutions in densities of 4M, 16M, and 64Mbit. All products are designed to operate from a single 3.3 volt supply. With data retention after each write of 20 years and infinite read/write endurance, Aeroflex MRAM products are ideal for working memory applications that require high rates of data overwrites.

Hitachi and Tohoku University have developed n STT-RAM that can be written using multi-level cell (MLC) technology. They actually call their technology SPRAM (spin-transfer torque memory).

The idea is to three-dimensionally stack two TMR elements and connect them in series. This creates , four-value memory (2 bits per cell). Hitachi has already produced a prototype of this memory. The biggest advantage of the MLC SPRAM is that it can reduce bit costs in proportion to the number of stacked TMR elements, Hitachi said. For example, when two TMR elements are stacked, bit costs are reduced by about half.

The US Defense Advanced Research Projects Agency (DARPA) has awarded Grandis with a $8.6 million 2nd phase project for STT-RAM chip development. The first phase ($6.0) was received in October 2008.

Phase 2 will focus on test of verification of STT-RAM integrated memory arrays.

Fujitsu Laboratories has developed a new memory cell circuit for STT-MRAM that reverses the typical order of magnetic tunnel junctions (MTJ) to enable a space savings of 60% and achieve a greater degree of integration

The memory cell circuit in spin-torque-transfer MRAM is a circuit that connects the MTJ element with a cell-select transistor, which act as switches that select which MTJ elements to write to or read from. With existing memory cell circuits, when the MTJ element of a spin-torque-transfer MRAM has been written to a high-resistance state ("1"), voltage is lowered through variable resistance - this requires a larger current to write than when an MTJ element it is switched to a low resistance state ("0"), which is not affected by variable resistance. In other words, because the cell-select transistor's current-driving capability is low, writing to a high-resistance state ("1") would require a significant current. As such, even with a low driving-current capability, cell-select transistors need to be relatively large to ensure an adequate write current, which has been a barrier to reducing transistor size.

Menta SAS and LIRMM (The Montpellier Laboratory of Informatics, Robotics, and Microelectronics) has confirmed the tape out of world’s first MRAM-based FPGA. The FPGA is based on Menta's eFGPA Core programmable logic architecture and on CEA-LETI and Crocus's MRAM technology. It is manufactured in CMOS 130nm with magnetic junction in 120nm and provides capacity of 1,444 LUT4, equivalent to approximately 20K logic gates.

Pr Lionel Torres, in charge of the MRAM design project at LIRMM, says that “MRAM-based FPGA proposes better versatility with partial or dynamic re-configurability capabilities, instant on/off total or partial energy saving”.

Researchers have designed a new kind of magnetic memory called frequency-controlled magnetic vortex memory. It takes advantage of magnetic vortices' ability to store binary information as positive or negative core polarities, which can be controlled by simply changing the frequency of the rotating vortex cores of the nanodots.

The concept of using magnetic nano-objects to store information for magnetic-RAM is already known, but it’s been difficult to find a mechanism to reverse the magnetization inside individual nano-objects. The researchers achieved this reversal by using microwave pulses in combination with a static magnetic field. In this scheme, large and small rotating core frequencies are associated with positive and negative core polarities, respectively. In a positive core polarity, the core is parallel to the applied magnetic field, while in a negative core polarity, the core is antiparallel to the applied magnetic field. An extremely sensitive magnetic resonance force microscope (MRFM) is used to address the resonant frequency of magnetic nanodots’ vortex core rotations, allowing the researchers to control the polarity states of individual nanodots.

Everspin has announced a new MRAM chip (MR4A16B) with 16-megabit (Mb) density. Samples are available now, and mass-production will begin in July 2010. There are two options for the chips: commercial chips and industrial chips (that have a larger temperature range: -40°C to +85°C). Everspin also promises to continue and deliver MRAM at increasingly higher densities.

Everspin MR4A16B

This is the first time since the MRAM chips were introduced by Freescale in 2006 that they announce higher-density chips.

A group led by Professor Hideo Ohno in the Laboratory of Nanoelectronics and Spintronics, at Tohoku University is working to develop new integrated circuits using spintronics. The ICs store data in nonvolatile memory using magnetism, so their standby power can be made zero. This memory utilizes the tunnel magneto-resistance effect.

Osaka's university has a Spintronics research group that is working towards MRAM and STT-RAM using several materials including Graphene. Here's a nice intro video about the group: