Hitachi and Tohoku University have developed n STT-RAM that can be written using multi-level cell (MLC) technology. They actually call their technology SPRAM (spin-transfer torque memory).
The idea is to three-dimensionally stack two TMR elements and connect them in series. This creates , four-value memory (2 bits per cell). Hitachi has already produced a prototype of this memory. The biggest advantage of the MLC SPRAM is that it can reduce bit costs in proportion to the number of stacked TMR elements, Hitachi said. For example, when two TMR elements are stacked, bit costs are reduced by about half.
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Posted: Jun 23,2010 by Ron Mertens
