Technical / Research

Researchers from Korea's Ulsan National Institute of Science & Technology (UNIST) have designed a new MRAM structure, based on graphene, that offers higher efficiency (and lower heat generation) compared to existing MRAM solutions.

The design of the MRAM device is based on a graphene layer sandwiched between a magnetic insulator (yttrium iron garnet) and a ferroelectric material (PVDF-TrFE). Upon application of a voltage pulse, the current flow through the graphene is altered, enabling the storage of binary data based on this current direction.

Hprobe, a developer of testing equipment for magnetic devices, announced a strategic collaboration with NY CREATES, a lab-to-fab bridge for advanced electronics, to advance testing capabilities for next-generation semiconductor memory technologies. This joint development project will focus on the co-development of advanced testing equipment at the 300mm wafer scale.

NY CREATES and Hprobe will work together to support new testing solutions for MRAM, RRAM and selector devices. The joint project will focus on initial testing of MRAM and RRAM wafers from NY CREATES using Hprobe’s equipment, including the full-scale implementation of Hprobe’s IBEX wafer-level magnetic tester. Development of breakthrough testing procedures and algorithms for MRAM, RRAM, and selector devices, will also seek to advance the state-of-the-art in semiconductor memory testing.

Kioxia Corporation (Toshiba's memory unit that was spun-off in 2021), in collaboration with SK Hynix, announced that it has developed the world's smallest 1Selector-1MTJ cell.

Kioxia says that the two companies have demonstrated a reliable 1 selector-1 MTJ (1S1M) cell read/write operation with low read disturb rate of <1E^-6 in 64 Gb cross-point array architecture. They have implemented cross-point 1S1M chips integrated in Half Pitch (HP) of 20.5 nm and MTJ CD of 20 nm using As-doped SiO2 selector and perpendicularly magnetized MTJ (p-MTJ).

Researchers from  Purdue University were awarded with a new project to advanced AI using research performed at Purdue for over a decade. The CHEETA:CMOS+MRAM project will utilize a CMOS+X approach specifically leveraging the unique capabilities of MRAM memory to design efficient in-memory computing hardware fabrics.

The CHEETA project aims to deliver impactful improvements in energy efficiency and sensor-to-decision latency compared to the current commercial standard. The project received funding from the Applied Research Institute. 

Researchers from the Institute of Science Tokyo (formerly Tokyo Tech), in collaboration with Western Digital, has developed a new high-performance material suitable for low-power SOT-MRAM.

The researchers are using BiSb material under the CoFeB/MgO, with perpendicular magnetic anisotropy. By optimizing the interfacial layer thickness as well as deposition condition of BiSb, the researchers managed to achieve a large effective spin Hall angle and relatively high electrical conductivity. The researchers continued to demonstrate spin–orbit torque-induced magnetization switching driven by a small threshold current density.

The New York Center for Research, Economic Advancement, Technology, Engineering, and Science (NY CREATES) and CEA-Leti announced a two-year strategic R&D partnership, that will initially focus on the research and co-development of MRAM devices.

NY CREATES and CEA-Leti will develop and produce both STT-MRAM and SOT-MRAM devices on 300 mm substrates. CEA-Leti will contribute its expertise in magnetics, spintronics, and the testing of related devices, and NY CREATES will provide the facilities, process integration expertise, and materials process development to run the 300mm silicon hardware.

High-performance STT-MRAM developer Numem announced that in collaboration with ASIC/SoC designer IC’ALPS it has developed an integrated circuit with RISC-V processors, 2MBytes of NuRAM and a DSP/AI Custom Datapath Accelerator.

The two companies co-developed the SoC in an advanced technology node, taking advance of the high-performance and low power consumption of Numem's memory technology. The company also details that the physical implementation of this integrated circuit was made in a secure space (isolated location, network, and servers, and encrypted exchanges) to meet with the stringent protection of sensitive data required by this program. Numem and IC’Alps intend to extend their partnership to serve new SoC projects for customers.

Researchers from Northwestern University, led by Prof. Pedram Khalili, report the first all-antiferromagnetic tunnel junction (ATJ) devices with both electrical switching and electrical readout of the antiferromagnetic state. The researchers observed a large room-temperature tunneling magnetoresistance effect that is comparable in size to conventional ferromagnet-based tunnel junctions. 

To create the new devices, the researchers used sputtering to deposit the device films on conventional silicon wafers. The films are compatible with established semiconductor manufacturing processes. 

Renesas Electronics announced that it has developed circuit technologies for embedded STT-MRAM that reduces the energy and voltage of the memory write operation. 

Renesas produced a 22-nm MCU test chip, that includes a 10.8 Mbit embedded MRAM memory cell array. It achieves a random read access frequency of over 200 MHz and a write throughput of 10.4-megabytes-per-second (MB/s).