Technical / Research - Page 19

Renesas has released a presentation about their flash memory products, which also includes one slide about their  flash memory roadmap. The roadmap includes Floating Gate HND (Hyper New DINOR), MONOS (metal Oxide Nitride Oxide Silicon) and also MRAM.

They plan to have 100 to 150Mhz MRAM at 90nm at around 2010, and 200Mhz MRAM at 65nm at around 2012. They say MRAM is the next-generation RAM, a breakthrough beyond the limit of flash memory.

Fujitsu Laboratories and the University of Toronto announced that they have jointly developed the world's first high-reliability read-method for use with spin-torque-transfer (STT) MRAM that is insusceptible to erroneous writes.

STT-MRAM circuit embedded in a CMOS chip

The newly developed read-method uses a negative resistance that is intermediate between the MTJ's high resistance and low resistance on a parallel circuit. If the MTJ is in a high-resistance state, this circuit exhibits negative-resistance characteristics. If the MTJ is in a low-resistance state, then it exhibits normal-resistance characteristics. These characteristics allow the resistance value to be read at lower voltages than before, suppressing the tendency of the read operation to reverse the direction of magnetization and avoiding the problem of erroneous write operations.

Fujitsu Laboratories and the University of Toronto plan to continue with R&D related to STT MRAM to strive toward practical implementation, such as lowering write currents and developing process technologies for further miniaturization.

NVE says that they have completed several custom anti-temper MRAM integrated circuit designs. NVE designs conventional semiconductor ICs which they fabricate at outside foundries. Then they add the Spintronic structures, in this case spin-dependent tunnel junction memory cells, in their own factory.

NVE now reveals that they have received a number of the foundry wafers they have designed and they are in the process of adding MRAM to the wafers. The prototypes look promising so far although a fair amount of development remains before production.

Researchers from Japan's AIST institute have developed a new Tunnel-Magnetoresistance (or TMR) element with a low data writing current and high data stability. This kind of TMR is required for high-capacity MRAM. In fact the team says that this TMR can be used to make perpendicular STT-MRAM with densities of over 10GBit.

With existing TMRs, there's a trade-off between data writing current and data stability. Data loss happens if the free-layer's magnetization is reversed because of thermal agitation, and if you make a thicker free-layer it solves the data-loss issues, but you need more current. The new design solved this issue by using a free layer that is made from a nonmagnetic layer between two ferromagnetic layers. The resistance to thermal agitation is improved - it is five times better, while the current is only increased by 80%.

The team used an in-plane magnetization film for the free layer, which can be used to make a 1-Gbit MRAM. They plan to make the current even lower with a perpendicular magnetization film, which will allow for a 10 Gbit MRAM device.

France has launched a large Spintronics project, with a 4.2M euro investment. It's called SPIN, and involved 11 partners. One of the project goals is magnetic FPGAs. Here's how they describe it:

The objective will be to design a magnetic FPGA which will incorporate finely distributed Magnetic Tunnel Junctions (MTJs) for non volatile storage and configuration purposes above of a CMOS core circuit. In complement of existing high density FPGAs, it will provide better versatility with intrinsic reconfigurability, instant on/off and energy saving. Such FPGAs can be used as general purpose standalone products. In the SPIN project, the FPGA will be targeted to provide intelligent processing of the magnetometers and sensors developed in objectives 2 and 3. 

More information can be found here.

The Korean Government has decided to fund STT-RAM research for Hynix and Samsung in a $40 million project. The government will pay around half of the sum for the project, which is intended to run till 2014. The project calls for the government to work with Samsung and Hynix together for research and development on STT-MRAM chips. Korea aims to control around 45% of the 30-nano type memory chip market by 2015.

The companies have already opened a new laboratory at Hangyang University's fusion technology center. It is already equipped with a fully operational 300mm magnetic thin film deposition system and other chip-making facilities.

Everspin is introducing a new family of MRAM products, with a Serial Peripheral Interface (SPI) bus. The new family is called MR24H and includes 256Kb, 512Kb and 1Mb products. These Everspin MRAM devices require no write delay, run at clock speeds as fast as 40 MHz and have unlimited endurance with more than 20 years data retention. 

The MR25H256 (256Kb), MR25H512 (512Kb) and MR25H10 (1Mb) serial MRAM products operate from  2.7 to 3.6 volts while offering low standby and operating currents as well as a 3 uA (typical) sleep mode to further improve the system power consumption. They are byte-organized internally, containing 32KB, 64KB and 128KB of data respectively. Industry-standard serial SPI command codes and timing enable easy connection to existing MCU and system designs. The devices are housed in low profile 8-pin RoHS-compliant DFN packages that are pin-out and footprint compatible with serial EEPROM, Flash and FeRAM products in comparable DFN or SOIC packages.

Spingate is a new US-based fabless company focusing on development, licensing and manufacturing of solid state memory, specifically, perpendicular MRAM.

We have talked to Dr. Alex Shukh, Spingate's co-founder, CTO and CEO. Alex explains that they have decided to focus on perpendicular MRAM because according to their estimates it does not suffer from several fundamental issues of its longitudinal (in-plane) analogue.

However, to be successful with p-MRAM development, Spingate needs to solve several serious problems, such as, a reduction of energy consumption during writing, development of new magnetic materials with perpendicular anisotropy for storage and reference layers exhibiting high GMR, etc.

Spingate's IP portfolio already includes one granted and several pending patents on p-MRAM, which covers multi-bit cell, 3D-memory designs, etc. The proposed solutions should close existing cell density gap between MRAM and Flash since 2D-Flash won't be able to compete with 3D-MRAM. Spingate are currently working on cell design development and optimization, and is looking for investors.

Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, say they have developed an MRAM-based FPGA circuit.

They use Thermally Assisted Switching (TAS)-MRAM with a small current for heating the Magnetic Junction Tunnel, allowing a higher sensitivity to magnetic fields. The magnetic field is induced by a current line above or below the junction depending on the technology.

Micromem says that their Memory (MRAM) product is now complete through the Global-Communication-Semiconductor and BAE Systems foundries. The MRAM is fully packaged in arrays, and it's being tested and evaluated against standard and routine memory tests.