Hitachi, Ltd. and Prof. Hideo Ohno of The Research Institute of Electrical Communication, Tohoku University have jointly prototyped a 2 Mbit nonvolatile RAM chip based on the spin torque transfer writing technology. When a 1.8 V voltage is supplied, the write and read times are 100 and 40 ns, respectively. TMR elements used in the chip were produced by the Tohoku Univ. lab while the chip designed with a 0.2 ?m rule process technology was manufactured by Hitachi. The details were presented at the ISSCC 2007 event being held in San Francisco on February 14 (US time).
The nonvolatile RAM based on spin torque transfer is designed to eliminate write lines for magnetic field generation used in a magnetoresistive RAM (MRAM). Instead, data rewriting is performed by the current flown through memory elements (TMR elements). In this way, the spin torque transfer RAM can solve a problem of the write current in MRAM which increases as miniaturization accelerates. Thus far, Hitachi and Tohoku Univ. have jointly examined the principles of this method at the element level.
The write current of the prototyped RAM is 200 ?A/cell, lower than that of a standard MRAM. It was demonstrated that data can be rewritten 109 times with a 100 ns pulse current. The chip measures 5.32 x 2.5 mm. The cell size is 1.6 x 1.6 ?m, which is equivalent to 16F2 (F is the design rule of cell section which equals to 0.4 ?m). This is smaller than a standard MRAM cell. It is reported that 10F2 is also feasible by improving the design layout. The magnetoresistance ratio of the TMR element is approximately 100. Incidentally, Sony Corp. presented a prototype of 4 Kbit Nonvolatile RAM based on spin torque transfer at the 2005 IEDM event. The capacity of the latest MRAM is nearly three orders of magnitude larger than that of Sony's product.
