Technical / Research - Page 8

In 2015, the EU launched the GREAT project, with an aim to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting STT-MTJs to a single baseline technology in the same system on chip. GREAT stands for heteroGeneous integRated magnetic tEchnology using multifonctionnal stAndardized sTack.

The project partners now announced the first hybrid CMOS/MSS-MRAM Tape Out with Israel-based Tower Jazz. This hybrid integrated circuit uses the 180nm CMOS process from Tower and an academic MRAM post-process that will be done by CEA Spintec within their facilities.

Researchers from the Trinity College in Dublin developed a new device using a stack of five metal layers (including a platinum layer and an iron-based layer) that can be used to control the spin of electrons - using "spin–orbit torque", or SOT, an alternative to spin-transfer torque (STT) - but without an external field.

The basic idea is that when a current is run through the platinum, the electrons split into two groups by their spin (that's the SOT effect). Electrons are inserted into the iron-based "storage layer" and the spin of those electrons can be changed. The rest of the layers act like a thin-film magnet which helps determine the spin of the electrons.

Researchers from the National University of Singapore (NUS) developed what they say is the world's first flexible (bendable, actually) MRAM device. Flexible OLED displays are already entering the market, and now researchers are developing other flexible components, which will be needed if truly bendable and flexible devices are to be possible.

The researchers used a new fabrication method, that enabled them to deposit the magnetic memory on a plastic substrate, and not a silicon one. This was achieved following a two-year collaboration with Yonsei University, Ghent University and Singapore's Institute of Materials Research and Engineering.

IBM researchers, in collaboration with Samsung researchers, demonstrated switching MRAM cells for devices with diameters ranging from 50 down to 11 nanometers in only 10 nanoseconds, using only 7.5 microamperes. The researchers say that this is a significant achievement on the way to high-density low-power STT-MRAM.

Using perpendicular magnetic anisotropy (PMA), the researchers can deliver good STT-MRAM performance down to 7×10^-10 write-error-rate with 10 nanosecond pulses using switching currents of only 7.5 microampere.

Mark Stiles, from the NIST's Center for Nanoscale science and technology, gave an interesting lecture titled "Spin Current: the Torque Wrench of Spintronics" in which he discussed spintronics challenges, especially for spin-torque memory devices:

Researchers from Israel's Bar Ilan University and New York University designed a six-state magnetic element - which could be used to create a magnetic memory device with six-states - and thus a higher density than a the regular 2-state device.

The researchers say that multi-level MRAM cells based on this design should not suffer from low writing speed and high power consumption - problems that are common in multi-level Flash memory cells.

Researchers from Japan's Tohoku University developed a technology to stack magnetic tunnel junctions (MTJs) directly on the the vertical interconnect access (via) without causing deterioration to its electric/magnetic characteristics. The researchers say that this technique can reduce the chip area of STT-MRAM.

The via in an integrated circuit design is a small opening that allows a conductive connection between the different layers of a semiconductor device. Placing the MTJ directly on the via holes has been avoided because it can degrade the MTJ's characteristics because the MTJ is very sensitive to the quality of the surface of its lower electrode.

Researchers at Tohoku University developed a new scheme of spin-orbit-torque (SOT) induced magnetization switching. In the new scheme the magnetization directed collinear with the current.

The researcher fabricated three-terminal devices with the new structure (using a Ta/CoFeB/MgO-based magnetic tunnel junction) and successfully demonstrated the switching operation. The research report a "reasonably small" required current density to induce the magnetization switching and a "reasonably large" resistance difference between 0 and 1 states. They say that this is a promising candidate for future MRAM devices.

Researchers from Eindhoven's University of Technology (TU/e) managed to use a bending current to change an MRAM "bit". The result is a much more efficient memory write cycle that is also faster than conventional MRAM methods.

The idea is to use a current pulse under the MRAM cell bit which bends the electrons at the correct spin upwards towards MRAM bit. This was achieved before, but using a magnetic field. In this new method, the researchers applied an anti-ferromagnetic material to the top of the MRAM bits, which enabled the requisite magnetic field to be frozen.

Researcher from Cornell's NanoScale Science and Technology Facility (CNF), in collaboration with Oxford Instruments Plasma Technology (OIPT) developed a new etching process targeted specifically for MRAM device fabrication.

The etching of the MTJ stack is a challenging step in MRAM fabrication, because the magnetic materials do not easily react to etching agents, and so manufactures usually use purely physical ion milling processes - which results in low etch rates, low selectivity and damage to the device structure itself.