Technical / Research - Page 7

Researchers from Japan's National Institute of Advanced Industrial Science and Technology (AIST) developed a new process, based on 3D stacking, that forms a single-crystal TMR device on a polycrystal metal wire.

The stacking process creates the TMR thin-film on a single-crystal silicon wafer and then bonds it to a CMOS on another wafer. This opens the way to using these materials in high-performance MRAM devices. The single-crystal TMRs reduces the variation in the device and can enable smaller TMRs. The researcher say that it will take up to 2 years to completely develop the new 3D stacking process.

In 2015, the EU launched the GREAT project, with an aim to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS by adapting STT-MTJs to a single baseline technology in the same system on chip. GREAT stands for heteroGeneous integRated magnetic tEchnology using multifonctionnal stAndardized sTack.

After the delivery of a first demonstrator in 2017, the project partners now announced the second hybrid CMOS/MSS-MRAM 180nm Tape Out at Israel-based Tower Jazz. The project partners designed four ICs to validate Analog IP blocks and an ultra-low power MCU comprising a hardware security block.

Spin Transfer Technologies (STT) announced that its unique Precessional Spin Current (PSC) structure can increase the spin-torque efficiency of any MRAM device by 40-70 percent, which means dramatically higher data retention while consuming less power.

Following advanced testing, the company says that these higher spin-torque efficiencies translate to retention times lengthening by a factor of over 10,000 while reducing write current.

Researchers from Tohoku University developed new ultra-small (single-digit nanometer scale) magnetic tunnel junctions (MTJs) that have sufficient retention properties and yet can be switched by a current.

Tohoku University developed 20-nm CoFeB/MgO-based MTJs in 2010, in which an "interfacial anisotropy" at the CoFeB/MgO interface was utilized. But these will not work at under 20-nm. The researchers now used a "shape anisotropy" to achieve the smaller MTJs.

Tohoku University's Center for Innovative Integrated Electronic System (CIES) announced that its collaboration with Keysight Technology has led to the release of a new MRAM test platform product, the NX5730A.

Keysight's NX5730A is a high-throughput 1 ns Pulsed IV memory test solution. Keysight says that this solution is a unique dedicated system for characterizing emerging devices such as magnetic tunnel junction (MTJ) on silicon wafers, accelerating the efficiency of device characterization and memory production testing.

Researchers from UC Berkeley and UC Riverside developed a new ultra-fast method for electrically controlling magnetism in certain metals. The researchers say that this could be applied to future MRAM chips, to provide much faster write speeds and more efficient operation.

The researchers built special circuits to study how magnetic metals respond to electrical pulses as short as a few picoseconds. The researchers found that in a magnetic alloy made up of gadolinium and iron, these fast electrical pulses can switch the direction of the magnetism in less than 10 picoseconds, orders of magnitude faster than any other MRAM technology.

The EU launched a new project called GREAT H2020 moderated by the CEA-Spintec laboratory that plans to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS thanks to a single baseline technology in the same System on Chip.

One of the project’s final objectives is to develop a system-level simulation and design of a representative IoT platform, integrating this technology. To achieve it, a unique exploration flow is proposed: MAGPIE. MAGPIE stands for Manycore Architecture enerGy and Performance evaluation Environment and has been jointly developed and funded through GREAT and the CONTINUUM ANR French project.

Researchers from Helmholtz-Zentrum Berlin developed a robust and reliable magnetization switching process - that could one day lead to highly efficient spintronics memory devices.

The researchers used domain wall displacement to switch between two possible vortex states - without any applied field. The basic idea is to use tiny tings which have slightly displaced holes.

Samsung demonstrated an LCD display that uses a tCON chip that uses embedded 28nm pMTJ STT-MRAM memory, instead of the normally used SRAM. The MRAM device had a density of 8Mb and a 1T-1MTJ cell architecture. The cell size is 0.0364 um².

A tCON chip is a timing controller chip that processes the video signal input and processes it to generate control signal to the source & gate driver of the LCD display. The memory is used a a frame memory which stores previous frame data. Samsung prepared a test chip that contains both SRAM and MRAM memory devices to show that there is no difference between the two. SRAM replacement is a popular MRAM application.

Researchers at IMEC developed a 8nm perpendicular magnetic tunnel junction (pMTJ) with 100% tunnel magnetoresistance (TMR) and a magnetic coercive field up to 1,500 Oe in strength. The researchers also demonstrated integrated 1Mbit STT-MRAM 1T1MTJ arrays with pitches down to 100 nm.

IMEC says that this is the world's smallest pMTJ - which paves the way for high density stand-alone MRAM applications. The pMTJ was developed on 300mm silicon wafers in a production process that is compatible with the thermal budget of standard CMOS back-end-of-line technology.