Renesas

Renesas Electronics announced that it has developed circuit technologies for embedded STT-MRAM that reduces the energy and voltage of the memory write operation. 

Renesas produced a 22-nm MCU test chip, that includes a 10.8 Mbit embedded MRAM memory cell array. It achieves a random read access frequency of over 200 MHz and a write throughput of 10.4-megabytes-per-second (MB/s).

Renesas Electronics announced that it has developed two new technologies that reduce the energy and voltage application time for the write operation of STT-MRAM chips.

On a 20-Mbit test chip with embedded MRAM memory cell array in a 16 nm FinFET logic process, a 72% reduction in write energy and a 50% reduction in the voltage application time were confirmed.

According to Nikkei, over 20 Japanese and US companies have teamed up to develop MRAM technologies, in particular a new mass production method. Participants in this ambitious project include Tokyo Electron (who's merging with Applied Materials), Renasas, Hitachi and Shin-Etsu Chemical from Japan and Micron Technology from the US.

Japan's Tohoku University, a leader in Spintronics and MRAM research, will also join the project. The companies will finance several dozens researchers at the University. They plan to start development in February 2014, and continue to seek more companies from the US and Europe to join. The aim is to complete materials and processes development by 2017 and start mass production by 2018.

Samsung announced that it has acquired Grandis, developer of STT-MRAM technology. We do not have any financial details yet, but Grandis' CEO Frahad Tabrizi said that this deal serves as a& "very successful exit" for Grandis's investors. Grandis raised $15 million since it was founded in 2002 (and also raised about the same from DARPA grants including a $8.6 million second-phase project granted in June 2010).

Grandis licensed their technology to several companies. We know that Hynix licensed it in 2008. The company was also collaborating with Renesas technologies. Hynix and Grandis were developing a compact in-plane MTJ based STT-RAM device that uses modified DRAM processes at 54nm.

Renesas has released a presentation about their flash memory products, which also includes one slide about their  flash memory roadmap. The roadmap includes Floating Gate HND (Hyper New DINOR), MONOS (metal Oxide Nitride Oxide Silicon) and also MRAM.

They plan to have 100 to 150Mhz MRAM at 90nm at around 2010, and 200Mhz MRAM at 65nm at around 2012. They say MRAM is the next-generation RAM, a breakthrough beyond the limit of flash memory.

Renesas plans to start shipping MRAM samples in 2009. These products will be based on 90nm tech. Last month they said they will ship products in 2010. So samples in 2009, products in 2010. Renesas will also manufacture microcontrollers with embedded MRAM, also to be sold in 2010.

Renesas already has made 130nm MRAM, but they want to make it cheaper and with better power consumption, and this is why they're going to make then at 90nm. 

Renesas has announced the new R&D roadmap. The company plans to raise its development efficiency and provide high added-value products by reinforcing its design ability. The roadmap is primarily geared towards hardware IP. Memory IP is in there, including flash memory and MRAM.

Read more here (TechOn)

Renesas claims to have already devised a 130-nm MRAM, which is a four-level-metal technology with a cell size of 0.81-micron² and a standby current of zero.

But on its roadmap, the company will first commercialize an MRAM product, based on 90-nm technology that operates from 100-to-150-MHz. Slated for 2010, the device is geared for embedded memory applications in the company's core microcontroller market, said Katsuhiro Tsukamoto, president and chief operating officer at Renesas.

In addressing the need for next-generation high-density on-chip non-volatile memory Technology, Hitachi, Ltd. and Renesas today announced the development of a 512-kbyte (4-Mbit equivalent) phase change memory module operating at a 1.5-V power supply voltage, which achieves 416-kbyte/sec high-speed write and read speeds with a 20-nanosecond access time. Using the previously developed "low-power phase change memory cells" with a 100-uA (micro(2)-ampere) write current, the two companies developed a peripheral circuit Technology to enable the high-speed write and read operations.

An experimental 512-kbyte memory module was fabricated using a 130-nm CMOS process, employing the newly developed circuit Technology for cells writable at 100 uA. Test results confirmed the possibility of 416-kbyte/sec write operations and 20-nanosecond read operations, and high-speed operation was achieved while maintaining the Performance of low-power-operation phase change memory cells.