STT-MRAM: Introduction and market status - Page 4

pMTJ STT-MRAM developer Avalanche Technology announced that NexAIoT has adopted the company's 8Mbit MRAM (P-SRAM) products in its new fanless NISE & NIFE series industrial computers.

NexAIoT says that Avalanche's P-SRAM non-volatile memory provides the performance and reliability needed for its computers. The P-SRAM helps prevent data loss during power failures.

pMTJ STT-MRAM developer Avalanche Technology announced its third-generation 1Gb space-grade parallel asynchronous x32-interface high-reliability P-SRAM (Persistent SRAM) memory devices. The company says that these new devices enable customers to design unified memory architecture systems for high reliability aerospace applications, in extremely small form factors.

Avalanche's 2nd-Gen P-SRAM evaluation kit

The new Parallel x32 Space Grade series is offered in 512Mb, 1Gb, 2Gb and 4Gb density options and has asynchronous SRAM compatible 45ns/45ns read/write timings. Data is always non-volatile with >10^14 write cycles endurance and 10-year retention at 125°C. All four density options are available in a small footprint 142-Ball FBGA (17mm x 11mm) package.

pMTJ STT-MRAM developer Avalanche Technology announced that it is now shipping new space-grade parallel asynchronous x16-interface high-reliability P-SRAM (Persistent SRAM) memory devices, based on its latest STT-MRAM technology.

Avalanche says that its STT-MRAM devices are smaller and more efficienct compared to Toggle MRAM based products, currently adopted in aerospace applications. The Parallel x16 Space Grade series is offered in 16Mb, 32Mb and 64Mb density options and has asynchronous SRAM compatible 45ns/45ns read/write timings. All three density options currently in production and available within industry standard lead times.

Integral Solutions International (ISI) announced its first shipment of a commercial SOT-MRAM tester system. This new equipment was developed by integrating a commercial pulser with ISI's proprietary bias-tee and measurement electronics.

ISI says that the new tester system generates pulses as narrow as 300pS, suitable for R&D applications which require extremely narrow pulse widths. In parallel, ISI is also developing its proprietary Gen-4 Pulser System, which will provide high-throughput and cost-effective measurement solutions with the flexibility of testing either STT-MRAM or SOT-MRAM devices. The Gen-4 system is expected to be released in the fall of 2021.

Everspin Technologies announced its preliminary Q4 2020 financial results. Total revenues were $10 million, down from $10.1 million in Q3 and up from $9.7 million in Q4 2019. Net loss int he quarter was $1.6 million, but the company generated $0.6 million in cash flow - Everspin's second consecutive positive cash flow from operations quarter.

Looking at FY2020, Everspin's revenues increased 12.1% to $42 million. At the end of the year, Everspin had $14.6 million in cash and equivalents. In Q4 2020, the company also received its first royalty revenue from GF for embedded 22FDX process MRAM.

IBM announced that during the 2020 IEEE International Electron Devices Meeting (IEDM 2020), that is now being held virtually, its researchers will reveal the first 14 nm node STT-MRAM. IBM says that efficient and high-performance STT-MRAM systems will help to address memory-compute bottlenecks in hybrid cloud systems.

IBM says that the 14 nm node embedded MRAM which will be revealed is the most advanced MRAM demonstrated to date. It features circuit design and process technology that could soon enable system designers to replace SRAM with twice the amount of MRAM in last-level CPU cache.

Everspin Technologies announced its Q3 2020 financial results, with revenues of $10.1 million, up 10% from Q3 2019 ($9.2 million) but down $14% from Q2 2020 ($11.8 million). The company's net less was $3.9 million.

Looking at the balance sheet, Everspin reports a cash flow of $1 million in the quarter - this was the first quarter ever for Everspin to have a positive cash flow.

High-performance STT-MRAM developer Numem announced that it has been selected for a NASA AI project, for which the company will supply its Numem NuRAM MRAM-based Memory. Numem says its memory enables a 2-3x smaller memory area and 20x to 50x lower standby power compared to SRAM.

The project, titled “DNN Radiation Hardened Co-processor as companion chip to NASA’s upcoming High-Performance Spaceflight Computing Processor” will develop a reconfigurable DNN Engine with multiple compute units which can support a wide range of DNN models and frame rates.

Researchers from the National Taiwan University developed an ultra-high performance MTJ, using a superlattice barrier and half-metallic magnets. The so-called superlattice-MTJ can be the basis of a new class of STT-MRAM (which the researcher call SS-MRAM) that achieves ultra-low power RA and write operations, high writing speed and unlimited endurance.

SS-MRAM adopts a superlattice barrier that replaces the MgO layer used in common STT-MRAM. The MgO layer is unstable and also suffers from a very large RA which results in high power consumption for writing operations. The superlattice has higher spin polarization than MgO and so the SS-MARM can provides not only ultra-high MR ratio but also ultra-low RA for high-speed and low power writing.

pMTJ STT-MRAM developer Avalanche Technology announced that its new industrial-grade Serial (SPI) P-SRAM (Persistent SRAM) memory devices are now available. The Serial (SPI) memory devices are designed to be drop-in replacements to Cypress F-RAM and Everspin Toggle MRAM memory products.

The Series (SPI) series supports up to 50MHz clock rate in 1Mb and 4Mb density options, in two packages - 8-pin SOIC and 8-pin WSON. These use Avalanche's 40nm pMTJ STT-MRAM chips.