STT-MRAM - Page 11

Everspin announced that it has started shipping samples based on its perpendicular magnetic tunnel junction (pMTJ) ST-MRAM. The first chip is the EMD3D256MB - a 256Mb DDR device. This is Everspin's 3rd-gen MRAM technology.

The pMTJ ST-MRAM offers improved performance, higher endurance, lower power, and better scalability compared to previous MRAM and ST-MRAM products. The company (together with GlobalFoundries) is now focused on the production ramp of the 256Mb MRAM and is working on a scaled-down 1Gb version.

Yole Developpement says that the emerging Non-Volatile Memory (NVM) market is still small, generating only $53 million in sales in 2015. The market is still limited to niche markets due to the limited densities.

Yole sees the market growing very quickly, though, to reach $4.6 billion by 2021 - a CAGR of 110%. Yole says that the clear go-to market for emerging-NVM will be storage-class memory. High-capacity SCM applications will use either phase-change memory or RRAM memory, while applications that require high endurance and speed will adopt STT-MRAM memories.

Researchers from the Trinity College in Dublin developed a new device using a stack of five metal layers (including a platinum layer and an iron-based layer) that can be used to control the spin of electrons - using "spin–orbit torque", or SOT, an alternative to spin-transfer torque (STT) - but without an external field.

The basic idea is that when a current is run through the platinum, the electrons split into two groups by their spin (that's the SOT effect). Electrons are inserted into the iron-based "storage layer" and the spin of those electrons can be changed. The rest of the layers act like a thin-film magnet which helps determine the spin of the electrons.

IBM researchers, in collaboration with Samsung researchers, demonstrated switching MRAM cells for devices with diameters ranging from 50 down to 11 nanometers in only 10 nanoseconds, using only 7.5 microamperes. The researchers say that this is a significant achievement on the way to high-density low-power STT-MRAM.

Using perpendicular magnetic anisotropy (PMA), the researchers can deliver good STT-MRAM performance down to 7×10^-10 write-error-rate with 10 nanosecond pulses using switching currents of only 7.5 microampere.

Mark Stiles, from the NIST's Center for Nanoscale science and technology, gave an interesting lecture titled "Spin Current: the Torque Wrench of Spintronics" in which he discussed spintronics challenges, especially for spin-torque memory devices:

Researchers from Israel's Bar Ilan University and New York University designed a six-state magnetic element - which could be used to create a magnetic memory device with six-states - and thus a higher density than a the regular 2-state device.

The researchers say that multi-level MRAM cells based on this design should not suffer from low writing speed and high power consumption - problems that are common in multi-level Flash memory cells.

Researchers from Japan's Tohoku University developed a technology to stack magnetic tunnel junctions (MTJs) directly on the the vertical interconnect access (via) without causing deterioration to its electric/magnetic characteristics. The researchers say that this technique can reduce the chip area of STT-MRAM.

The via in an integrated circuit design is a small opening that allows a conductive connection between the different layers of a semiconductor device. Placing the MTJ directly on the via holes has been avoided because it can degrade the MTJ's characteristics because the MTJ is very sensitive to the quality of the surface of its lower electrode.

Everspin announced that it started shipping 256Mb ST-MRAM samples to customers. Everspin also plans to increase the density and sample 1Gb ST-MRAM chips later this year. The new chips demonstrate interface speeds comparable to DRAM, with DDR3 and DDR4 interfaces. Volume production is expected "soon".

The new EMD3D256 chips are based on Everspin's proprietary magnetic tunnel junction (pMTJ) spin torque technology - and the company expects the new technology to enable it to produce ST-MRAM in lower geometries - and higher densities beyond 1Gb in the future.

Everspin announced that IBM has demonstrated the company's Spin Torque DDR3 MRAM in the ConTutto platform in a Power8 system. IBM showed show how Everspin’s ST-MRAM operates as persistent memory, accelerating storage and server applications.

ConTutto is an IBM research configurable platform for innovation in the memory subsystem of an OpenPOWER node. The DDR3 interface on the Everspin Spin Torque MRAM makes it easy for developers to take advantage of the write speed and persistence of MRAM.

Researchers at Tohoku University developed a new scheme of spin-orbit-torque (SOT) induced magnetization switching. In the new scheme the magnetization directed collinear with the current.

The researcher fabricated three-terminal devices with the new structure (using a Ta/CoFeB/MgO-based magnetic tunnel junction) and successfully demonstrated the switching operation. The research report a "reasonably small" required current density to induce the magnetization switching and a "reasonably large" resistance difference between 0 and 1 states. They say that this is a promising candidate for future MRAM devices.