STT-MRAM - Page 12

Spin Transfer Technologies (STT) has successfully produced a working prototype STT-MRAM device. The company's advanced prototyping magnetics processing line at its facility in Fremont, California, is now fully operational.

STT's prototypes incorporate proprietary, performance-enhancing ‘spin-filtering’ technology, and were fabricated on industry standard CMOS wafers sourced from a high volume Asian foundry supplier. The prototypes are based on 60-nm perpendicular magnetic tunnel junction devices

STT-MRAM developer Avalanche Technology raised $23 million from Thomvest Ventures, Vulcan Capital, Rogers Venture Partners, and VTB Capital. The company also has a substantial debt facility in place with Horizon Technology Finance.

Avalanche say that they are now bringing their Spin-Programmable STT-MRAM (SPMEM) discrete products to Tier-1 OEMS and licensing their embedded solutions (AvRAM) to strategic partners. The company previous financing round was announced in July 2012.

A new report from Coughlin Associates says that in the near future we will see dramatic changes in the memory market as as fast non-volatile memories augment and eventually replace volatile memory.

MRAM (and STT-MRAM) annual shipping capacity will rise from 240TB in 2014 to between 15 and 35 PB in 2020. MRAM and STT-RAM revenues are expected to increase from about $300 million in 2014 to between $1.35 and $3.15 billion by 2020.

Integral Solutions International released a 5,000 Oe perpendicular magnet for WLA-3000, their wafer-level STT-MRAM analyzer. ISI says that this new magnet is optimally matched with its proprietary probe card interface to produce up to 5,000 Oe for the latest generation of STT-MRAM devices.

The new magnet increases maximum field while also improving z-field uniformity to +/- 0.25mm, while maintaining near zero remanence fields. It can also operate with 66% higher magnetic field duty cycle compared to the previous 3,000 Oe Perpendicular Magnet system.

Everspin and Aupera unveiled the world's first all-MRAM storage module in the M.2 form factor. Aupera's AupM001 is an M.2 MRAM module that incorporates Evespin's 64Mbit EMD3D064M ST-MRAM chips and a PCIe backhaul interface to enable higher-performing flash array systems.

AupM001's initial capacity is 32 MB, with higher capacities coming soon. AupM001 is currently used in Aupera’s All Flash Array system for parity check and as a hardware accelerated engine for specific applications that require low latency and high performance.

STT-MRAM developer Avalanche Technology announced that it began to sample STT-MRAM chips. Avalanche's proprietary perpendicular magnetic tunnel junction (pMTJ) cells are manufactured in a high volume, low cost, standard CMOS 300mm process.

Those first sample chips are 32Mbit and 64Mbit in size, and offer an industry-standard SPI interface built on a 55nm-node foundry process. Avalanche is also offering its STT-MRAM technology (which they brand as AvRAM) under license as embedded memory for integrated SOC designs.

Researchers from France's Universite Paris-Sud and the CEA institute say that the probabilistic nature of STT-MRAM devices can be used to create synapses-like neuro system. This can be used to create efficient devices that mimic the human's brain method of operation.

MRAM cells (or MTJs) store data using electrons magnetic spin. The technology uses stochastic switching, and so to be sure that a bit is set, you have to applying a current in the MTJ for a long enough time (to increase the probability of the spin changes).

Keysight Technologies announced it will launch STT-MRAM test solution products, developed in collaboration with Tohoku University and the Center for Innovative Integrated Electronic System (CIES).

Keysight says that they aim to release the test solution in early 2016. This will address "various challenges in industry".

Toshiba presented a new STT-MRAM 1-Mb test chip that provides speed performance capable of 3.3-ns access to in-cache memory. The newly developed circuit consumes about 80% less power compared to a conventional SRAM as embedded memory - and Toshiba says that this makes it the best power-performing embedded memory.

To make this chip, Toshiba developed a new class of magnetic materials, that enabled them to build this low-power, high-efficiency, high-speed performance in energy-efficient magnetic tunnel junction (MTJ) memory.

Yole Developpement released a new emerging-memory market report in which they try to asses the future of the memory market. Yose says that Phase-change memory (PCM) is pretty much dead, and the two main emerging memory technologies are MRAM and Resistive random Access Memory (ReRAM or RRAM).

While RRAM is very promising in the near future, with support from Micron (they plan to release RRAM chips in 2015) and Panasonic while other players are expected to react quickly. RRAM and STT-MRAM will compete in 2015-2016 in some standalone markets (such as embedded MCU, wearables and smart cards and the storage class memory for enterprise storage which will be the biggest market), and it's not clear yet which technology will be the most popular.