STT-MRAM

STT-MRAM (also called STT-RAM or sometimes ST-MRAM and ST-RAM) is an advanced type of MRAM devices. STT-MRAM enables higher densities, low power consumption and reduced cost compared to regular (so-called Toggle MRAM) devices. The main advantage of STT-MRAM over Toggle MRAM is the ability to scale the STT-MRAM chips to achieve higher densities at a lower cost.

STT-MRAM has the potential to become a leading storage technology as it is a high-performance memory (can challenge DRAM and SRAM) that can scale well below 10nm and challenge the low cost of flash memory.

What is STT-MRAM?

STT stands for Spin-Transfer Torque. In an STT-MRAM device, the spin of the electrons is flipped using a spin-polarized current. This effect is achieved in a magnetic tunnel junction (MTJ) or a spin-valve, and STT-MRAM devices use STT tunnel junctions (STT-MTJ). A spin-polarized current is created by passing a current though a thin magnetic layer. This current is then directed into a thinner magnetic layer which transfers the angular momentum to the thin layer which changes its spin.

Image
STT-MRAM structure diagram

What is perpendicular STT-MRAM?

A "regular" STT-MRAM structure (similar to the one you see above) uses an in-plane MTJ (iMTJ). Some STT-MRAM devices use a more optimized structure called perpendicular MTJ (pMTJ) in which the magnetic moments are perpendicular to the silicon substrate surface.

Perpendicular STT-MRAM is more scalable compared to iMTJ STT-MRAM and is also more cost competitive. Perpendicular STT-MRAM is thus a more promising technology to replace DRAM and other memory technologies

STT-MRAM chips

Several companies, including IBM and Samsung, Everspin, Avalanche Technologies, Spin Transfer Technologies and Crocus are developing STT-MRAM chips. In April 2016 Everspin announced that it started shipping 256Mb ST-MRAM samples to customers. The new chips demonstrate interface speeds comparable to DRAM, with DDR3 and DDR4 interfaces. Volume production is expected "soon".

Image
STT-MRAM chips

In August 2016 Everspin started sampling pMTJ-based ST-MRAM chips. The first chips are also 256Mb in size, but the pMTJ versions offer improved performance, higher endurance, lower power, and better scalability compared to previous iMTJ ST-MRAM products. Everspin is now ramping out 256Mb pMTJ ST-MRAM production and is developing a scaled-down 1Gb version.

 

 

Latest STT-MRAM news

Everspin names Phillip LoPresti as president and CEO

Everspin Technologies has named Phillip LoPresti its president and CEO.

“I am looking forward to building on MRAM’s success across multiple markets and leading Everspin through the next stage of our technology development,” said Phillip LoPresti. “Our strong product portfolio and proven track record positions us to expand market share as more customers recognize the value of our products. Everspin is focused on leveraging its MRAM expertise and resources to accelerate the introduction of new products in development based on our next-generation, high density Spin Torque MRAM technology.”

Read the full story Posted: Jul 14,2010

Everspin reported its Q4 2018 financial results

Everspin announced its financial results for Q4 2018. Revenues in the quarter grew 21% from last year to reach $12.3 million, while total year revenues in 2018 grew 38% from 2017 to reach $49.4 million. Net loss in the quarter was $3.5 million (down from $4.4 million in Q4 2017). Net loss for the whole 2018 was $17.8 million (down from $21.1 million in 2017).

Everspin says that it has increased the production volume of its 40nm 256Mb STT-MRAM in support of its lead flash array customer. Everspin ended 2018 with with cash and cash equivalents of $23.4 million.

Read the full story Posted: Mar 15,2019

Orthogonal Spin Transfer MRAM developer Spin Memory liquidates

Orthogonal Spin Transfer MRAM (OST-MRAM) technology developer Spin Memory is shutting down. The company's main investor and founding company, Allied Minds, said in a statement that the main reasons challenges in securing new customers and COVID-19 which "significantly delayed the required testing of its development chip with ARM".

MRAM by Spin Memory photo

This is a sad ending to Spin Memory, which began its way as Spin Transfer Technologies - a spin-off from NYU that was established together with Allied Minds.

Read the full story Posted: Jul 15,2021

A leading edge semiconductor maker orders a full suite of STT-MRAM metrology tools from MicroSense

MicroSense announced that they installed a full suite of STT-MRAM magnetic metrology tools at a leading edge semiconductor manufacturer. These metrology systems characterize the magnetic properties of multi-layer 300 mm wafers or coupons used in the development and manufacturing of Perpendicular and In-Plane STT-MRAM.

The company says that this is the first time a major customer ordered a full suite of their tools to use in an STT-MRAM program. This order includes a Polar Kerr system for 200mm or 300mm Perpendicular STT-MRAM wafers and a KerrMapper tool for 200mm or 300mm In-plane STT-MRAM wafers. MicroSense's EZ Vibrating Sample Magnetometer measures sample coupons from Perpendicular or In-Plane STT-MRAM wafers.

Read the full story Posted: Jan 15,2014

A new European project aims to develop a system-level STT-MRAM exploration flow

The EU launched a new project called GREAT H2020 moderated by the CEA-Spintec laboratory that plans to co-integrate multiple functions like sensors, RF receivers and logic/memory together within CMOS thanks to a single baseline technology in the same System on Chip.

MAGPIE process image

One of the project’s final objectives is to develop a system-level simulation and design of a representative IoT platform, integrating this technology. To achieve it, a unique exploration flow is proposed: MAGPIE. MAGPIE stands for Manycore Architecture enerGy and Performance evaluation Environment and has been jointly developed and funded through GREAT and the CONTINUUM ANR French project.

Read the full story Posted: Oct 12,2017

A*STAR patents low-density parity-check (LDPC) coding with soft decision decoding for STT-MRAM devices

A*STAR scientists have filed a patent on low-density parity-check (LDPC) coding with soft decision decoding. This is an advanced error correction coding scheme STT-MRAM devices. Hopefully this new scheme will enable more relaxed smaler STT-MRAM designs that can rely on the error-correction.

STT-MRAM devices suffer from cell errors due to imperfections in the fabrication process (variation in the tunneling oxide thickness and cross-section area). The researchers explain that conventional (hard decision) error correction codes do not work very well on STT-MRAM cells. The new soft decision decoding works on the probability of each detected bit as being a 0 or 1 (i.e. soft reliability), and hence has less decoding errors than the conventional hard decision decoding.

Read the full story Posted: Mar 15,2012

A*STAR researchers shed light on STT-RAM chip production temperature trade-offs

Researchers from A*STAR have posted an interesting study about STT-RAM production process. In particular, they say that it's already known that the annealing temperature controls the change in resistance between parallel and anti-parallel magnetizations. The higher the annealing temperature, the better larger the resistance change - but if the temperature is too high it drops.

The researchers now looked at an entire cell, and found out that the annealing temperature that yielded the maximum resistance variation exceeded the temperature necessary for maximum thermal stability.

Read the full story Posted: Aug 05,2012

Aupera Technologies launches the world's first storage module based on Everspin's pMTJ STT-MRAM

Aupera Technologies launched the world's first M.2 storage module based on Everspin's recently announced 256Mb pMTJ ST-MRAM. The Aup-AXL-M128, will be used in Aupera's All Flash Array system as a hardware acceleration engine for specific applications that require low latency and high performance.

Aupera Aup-AXL-M128 photo

Aupera says the company is excited at the future potential of this ST-MRAM based module. The ST-MRAM delivers four orders of magnitude BER reduction and more than 30% less power while quadrupling the capacity to 128MB as compared to the previous generation M.2 MRAM module.

Read the full story Posted: Aug 10,2016

Avalanche and ISI developed a new wafer level analyzer for STT-MRAM

Avalanche Technology and Integral Solutions International (ISI) have designed a Wafer Level Analyzer, the WLA-3000, to be used in STT-MRAM development.

The WLA-3000 includes specific hardware test modules including nS-range Pulse Generator that quickly measures switching currentse of MTJ devices in STT-MRAM as a function of Pulse Width. Using this Pulse Generator module, customers will be able to perform Error Rate, Switching Probability, Endurance Testing, and Read/Write Disturb analysis in a fraction of time as compared to other slower pulsers.

The WLA-3000 system is fully compatible with ISI’s FMRA-2008 Ferromagnetic Resonance Analyzer to offer the worlds most advanced and complete MTJ sensor analysis.

Read the full story Posted: Jul 09,2009