Technical / Research - Page 5

Researchers from the University of Arizona discovered that in common Magnetic Tunnel Junctions (MTJ), there's a thin (2D) layer of Iron Oxide. This layer was found to act as a contaminant which lowers the performance achieved by MTJs, but it may also hold the key to use antiferromagnetism in MRAM devices.

The researchers discovered that the layer behaves as a so-called antiferromagnet at extremely cold temperatures (below -245 degrees Celsius). Antiferromagnets are promising as these can be manipulated at Terahertz frequencies, about 1,000 times faster than existing, silicon-based technology. This is the first research that shows how Antiferromagnets can be controlled as part of MTJs and in the future may pave the way for its adoption in MRAM devices.

Researchers from Northwestern University suggest building STT-MRAM devices from antiferromagnetic materials - as opposed to the currently-used ferromagnetic ones. The researchers say that these materials will enable higher-density devices that feature high speed writing with low currents.

Antiferromagnetic materials are magnetically ordered at the microscopic scale, but not at the macroscopic scale. This means that there is no magnetic force between adjacent bits in MRAM cells built from these materials - which means you can pack them very close together.

Researchers from National Taiwan University demonstrate that chalcogenide material BiTe with non-epitaxial structure can give rise to a giant spin Hall ratio and SOT efficiency (~ 200%) without obvious evidence of topologically-protected surface state (TSS).

The researchers explain that a clear thickness-dependent increase of the SOT efficiency indicates that the origin of this effect is from the bulk spin-orbit interaction of such materials system. Efficient current-induced switching through SOT is also demonstrated with a low zero-thermal critical switching current density (~ 6×10⁵ A/cm²).

Researchers from the National University of Singapore (NUS) have identified a promising spintronics candidate material - few-layer thin semimetal molybdenum ditelluride (MoTe₂). When thinned to a few layer thickness, the MoTe₂ features excellent Spin Hall Effect properties.

The team now aims to incorporate MoTe₂ into functional devices - such as MRAM devices.

Researchers from Tokyo's Institute of Technology (Tokyo Tech) developed a new MRAM cell structure (called USMR MRAM) that features a very simple structure with only two layers - which could hopefully enable lower-cost MRAM devices.

The new design uses a combination of a topological insulator with a ferromagnetic semiconductor which enables a giant unidirectional spin Hall magnetoresistance (USMR).

Researchers from the National Taiwan University developed a new ultra low power STT-MRAM architecture, called Super Lattice STT-MRAM, or SL-STT-MRAM. The researchers say that SL-STT-MARM simultaneously achieves ultra-high MR ratio, high-speed switching, and low RA.

An SL-STT-MRAM is based on an SL-STT-MTJ, which uses a superlattice barrier to replace the single crystalline (MgO) barrier in traditional STT-MTJ. The superlattice barrier is made of alternating metal and insulator layers, in which only amorphous rather than single crystalline is used in the insulator. The SL-STT-MRAM features higher reliability for repeated writing than compared to traditional MgO based STT-MRAM.

Intel researchers have demonstrated 2MB STT-MRAM devices that are suitable for on-chip L4 cache applications. Intel says these devices feature data retention, endurance and bit error rates good enough for L4 cache.

Intel's new STT-MRAM features 20 nm write times, 4 ns read times, an endurance of 1012 cycles and memory retention of one second at 110 degrees. The bit rates are good enough to be handled with error-correcting code (ECC) techniques. To achieve these features, Intel reduced the magnetic junction size to 55 nm (from 70-80 nm it had achieved before).

Researchers at Tohoku University demonstrated a high-speed spin-orbit-torque MRAM (SOT-MRAM) memory cell compatible with 300 mm Si CMOS technology.

The SOT device achieved high-speed switching (down to 0.35 ns) and a high thermal stability factor (E/kBT 70) which the researchers say is sufficient for high speed non-volatile memory applications. The device can withstand annealing at 400°C. The researchers used these devices to create a complete SOT-MRAM memory cell.

Researchers from TU Dresden developed a novel memory device that is based on a combination of an light emitting material and a metal-oxide semiconductor (MOS) capacitor.

The so-called pinMOS device is a non-volatile memory-capacitor with high repeatability and reproducibility. pinMOS devices can store several states, since charges can be added or removed in controllable amounts. This device can also be controlled (read and write) both electrically and optically. The light emitting material is an OLED device.

Researchers from the Moscow Institute of Physics and Technology developed a new MRAM architecture that is based on THz pulses which are used to change the spin state. This so-called optically-assisted MRAM is extremely efficient (the power required to switch a "bit" will be a thousand times smaller compared to current MRAM devices) and fast.

The researchers use picosecond-long pulses (3 picoseconds = one light oscillation cycle) on a specially developed structure comprised from micrometer-sized gold antennas deposited on a thulium orthoferrite sample. The researcher admit that the material is excellent for fundamental research, but it may be too early to tell whether it could be used in the future for commercial applications. The researchers tell us that they re trying to raise funds now to start fundamental studies of this new optically-assisted MRAM.