Technical / Research - Page 12

The US Intelligence Advanced Research Projects Activity (IARPA) awarded Crocus with a contract to develop 8-bit per cell MRAM technology. This is the first phase in a multi-bit cell development project that is scheduled to be completed in one year.

Crocus will expand its magnetic logic unit (MLU) architecture to enable 8-bit per cells. This will reduce the energy consumed per written-bit to be below any other technology currently available. Such MRAM chips will be used to enhance chip security and cryptoprocessors as hacking into those chips will be more complex.

Researchers from the US Ames Laboratory in collaboration with Iowa State University and Greece's University of Crete developed a new way to switch magnetism that is at least 1000 times faster than current technologies. This all-optical quantum method may lead towards terahertz (or even faster) MRAM devices and faster hard drives.

The new technology uses short laser pulses to change the magnetic structure (from anti-ferromagnetic to ferromagnetic ordering) in colossal magnetoresistive materials (CMRs).

Researchers from the University of Cambridge in the UK have developed the world's first 3D microchip, based on Spintronics technology. The chip basically uses atoms to store and transfer the data - and not electronic transistors. This may lead to 3D MRAM chips that have a large memory density - thousands of times larger than what's available today.

To create this chip they used sputtering - effectively making a sandwich on a silicon chip of cobalt, platinum and ruthenium atoms. The cobalt and platinum atoms store the digital information in a similar way to how a hard disk drive stores data. The ruthenium atoms act as messengers, communicating that information between neighboring layers of cobalt and platinum. Each of the layers is only a few atoms thick.

Qualcomm and Belgium's Imec research center announced an extended collaboration agreement to accelerate scaling technologies for logic and memory devices, and Qualcomm will become a core partner of imec. This new agreement involves CMOS research and a new MRAM program.

We already know that Qualcomm is involved with MRAM research, but this is the first official announcement. Back in November 2012 Imec announced STT-MRAM collaboration with Tokyo Electron and Canon Anelva.

UCLA researcher have managed to make major improves in MRAM memory by electric voltage instead of a flowing electric current (which is used in STT-MRAM). They call the new memory MeRAM (Magnetoelectric Random Access Memory). The researchers say that MeRAM combines extraordinary low energy with very high density, high-speed reading and writing times, and non-volatility.

By using voltage to write data into MeRAM's memory, there's no need to move large numbers of electrons through wires and so the writing generates much less heat - in fact MeRAM could be 10 to 1,000 times more energy-efficient than STT-MRAM. It's also five times as dense (more bits stored in the same physical area). This should hopefully make MeRAM cheaper, too.

Toshiba has developed a prototype memory element for STT-MRAM that (according to Toshiba) achieves the world's lowest power consumption yet reported. STT-MRAM based on this element has the potential to surpass the power consumption efficiency of SRAM as cache memory.

Toshiba's improved structure is based on perpendicular magnetization and takes element miniaturization to below 30nm. Introduction of this newly designed "normally-off" memory circuit with no passes for current to leak into cuts leak current to zero in both operation and standby without any specific power supply management. The company says it improved the speed of their previous design - while reducing the power consumption by 90%.

Back in June 2010 We learned that Qualcomm is developing MRAM technologies. Now Qualcomm's QTI Advanced Memory Team posted a job opening that details a mobile STT-MRAM lead technologist - that will lead the development of next-generation mobile SOC memory subsystems that integrate Perpendicular STT-MRAM.

Last week Everspin announced their first ST-MRAM product, and today we found this nice video showing a tour of Everspin's booth at LSI AIS 2012 and explaining the company's technology and products. The explanation is given by Joseph O'hare, Everspin's director of product marketing:

Spingate announced that they invented a multi-bit Spin-RAM, which can store two bits per MTJ. It uses magnetic materials with perpendicular anisotropy and has a cell size of 4F², which is the smallest currently reported in the industry. This kind of memory can provide a density of about 160 Gbits/in² (0.257 Gbit/mm²) at 45 nm. They say their design has excellent thermal stability, and so can scale down to 10 nm.

Spingate's Spin-RAM uses the company's proprietary hybrid write mechanism based on a simultaneous application of a spin-polarized current and a bias magnetic field. The hybrid write mechanism provides the Spin RAM with a high switching speed (about 1 ns or less), low density of the spin-polarized current (about 10⁶ A/cm² or less), excellent endurance (about 10¹⁵ or above) and error rate. Spingate says that it can be smoothly arranged in a 3D architecture (without additional layers or selection transistors), and 1 Tbits/in² can be achieved at 25 nm (with only two layers of MTJ) or at 18 nm (in a 2D architecture).

Imec and Tokyo Electron (TEL) have decided to extend their current collaboration to include joint R&D on STT-MRAM, which will take place within imec’s research and development program on emerging memory technologies.

TEL installed a Tactras etch tool at imec's 300mm clean room. This enables imec and TEL to jointly develop the patterning processes for high-density STT-MRAM technology. The Tactras is designed for in-situ cluster patterning of the Magnetic Tunnel Junction (MTJ) stack, which is key for advanced memory technology nodes.