Crocus Technology announced the development of a new STT-MRAM technology with a minimum feature size of 50nm that will deliver on the promise of using STT memory in high-density memory
applications, that will be competitive with DRAM and NOR-Flash.
Researchers from NY University, together with Spin Transfer Technologies have demonstrated magnetic vector switching for current pulses as short as 100 picoseconds. This is among the shortest write times reported by developers of MRAM devices.
The underlying technology is based on a unique orthogonal orientation between the magnetic vectors in two magnetic layers -- a pinned magnetic layer where the magnetic orientation is fixed and a free magnetic layer where the magnetic field is aligned in one of two directions, thereby storing one bit of binary information. In contrast, all other MRAM efforts involve magnetic vectors that are both parallel to the physical layers or both perpendicular to the layers. Termed Orthogonal Spin Transfer MRAM (OST-MRAM), the technology results in a deterministic switching behavior, which enables high speed and very low power device operation. Other approaches result in stochastic switching which involves thermal fluctuations to initiate or hasten the switching process, leading to an incubation delay and requiring higher power for operation.
In addition, the OST-MRAM technology allows the use of magnetic tunnel junctions to achieve large read-out signals, while maintaining the advantages of deterministic switching and low power operation. Another key aspect of the technology is that it does not require sophisticated processes, such as magnetic annealing, for the fabrication of devices. This will significantly lower the cost of future commercial devices based on OST-MRAM technology, compared to other MRAM devices currently in development.
Back in October 2008, we have talked to Vincent Chun from Spin-Transfer-Technologies, and he explained their tech and plans.
The final day of the Flash Memory Summit started with a panel on new memory technologies.
Crocus Technologies presented their TAS MRAM design which is targeted at SRAM and flash applications. Their product compared to SRAM at a 25% smaller cell, adding Non-Volatile capability, and a zero standby current. The product compared to NAND flash by having a smaller cell and only 1X area overhead for controlling circuitry. It is currently being built on a 130nm node and can be scaled. It is targeted at Cache memory, data logging, medical instrumentation, casino gaming and industrial control applications. They are targeting several business models - selling the standard product ICs, licensing IP a process technology licensing service and providing a foundry service.
Avalanche Technology and Integral Solutions International (ISI) have designed a Wafer Level Analyzer, the WLA-3000, to be used in STT-MRAM development.
The WLA-3000 includes specific hardware test modules including nS-range Pulse Generator that quickly measures switching currentse of MTJ devices in STT-MRAM as a function of Pulse Width. Using this Pulse Generator module, customers will be able to perform Error Rate, Switching Probability, Endurance Testing, and Read/Write Disturb analysis in a fraction of time as compared to other slower pulsers.
The WLA-3000 system is fully compatible with ISIâs FMRA-2008 Ferromagnetic Resonance Analyzer to offer the worlds most advanced and complete MTJ sensor analysis.
A couple of days ago we reported that NEC are working towards perpendicular MRAM using 2T1MTJ... now we have some more info, thanks to TechOn.
NEC and NEC Electronics employed a new method called "spin torque domain wall displacement write method" to reduce write current and realize microfabrication at the same time. In fact, they aim to reduce the current by as much as 90%. They were also able to increase speed to 500Mhz. This technology is not 'new', it was announced in 2007, but now they have a test chip ready.
NEC announced that they have developed the world's first STT-MRAM with current-induced domain wall motion using perpendicular magnetic anisotropy material. Perpendicular magnetic anisotropy enables a cell to carry out the current-induced domain wall motion writing method using spin torque at a low current, which leads to easy scaling down of cell size and creates suitable conditions for next generation system LSI.
The newly developed current-induced domain wall motion writing method, using spin torque and perpendicular magnetization material, is capable of reducing current while writing for a scaled down cell beyond the 55 nanometer process.
Crocus announced today that it has implemented CIPtech, the newest tool
from CAPRES A/S, for enabling measurements associated with advanced Spin
Torque Technology (STT). This unique new tool,
designed especially for the MRAM and magnetic recording Read Head
industries, enables Crocus to determine tunneling resistance on MTJ
films prior to final test. With this upgrade, measurement that used to
require weeks of sample preparation can now be performed within minutes.
The CIPTech platform is used for measuring the critically important tunneling resistance and magneto-resistance (RA MR) directly on blanket magnetic tunnel junction (MTJ) films for MRAM (Magnetic Random Access Memory) and magnetic recording Read Head applications. The latest vertical magnetic field capability of the tool allows characterizing next-generation MRAM devices based on Spin Torque Transfer (STT). With this tool, Crocus is now equipped for efficient prototyping and manufacturing of advanced STT.
As we reported last month, Crocus is planning to have MRAM products by the end of the year, and are also working on STT-RAM.
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There's a new STT-RAM startup called Avalanche Technology (from California, US) that plans to commercialize 65nm standalone STT-RAM within 2 years.
Jean-Pierre Braun, the CEO of Crocus technologies, is visiting Israel these days, and I had the good chance of meeting him. Crocus' technology is based on work done by the French Spintec research center. In fact they get an exclusive access to Spintec MRAM related research and patents for the next 15 years.
Crocus' basic technology is based on Field-Induced MRAM (Toggle MRAM), which is in some ways similar to Everspin's technology (or 1st generation MRAM). Historically, Field-Induced MRAM is very hard to scale, and has stability and retention problems. Crocus aims to solve all this using a thermally activated magnetic latch. They call their technology Thermally Assisted Switching or TAS. Basically this means that the latch helps the cell retain the memory value very well. It can also scale quite well. This also (theoretically) will allow them to pack more than 1 bit per cell... some day.
Jean-Pierre says that many companies are doing 'Thermal MRAM' - which only means heating the material for easier handling. But Crocus technology is very different - because of the use of this magnetic latch, not just heat by itself.
Crocus already has a 'small' (few KBits) working sample of their memory, and towards the end of 2009 they will hopefully get a real product out. I can't say much yet, but this product will have a higher-density than Everspin's products (currently 4Mbit), smaller size and will also be considerably cheaper. This is great news, and hopefully they'll be able to pull it off. Even though the largest MRAM market is for embedded memory, the first Crocus product will be stand-alone.
Obviously these are hard times - especially for start ups and companies that are still losing money. Crocus has already raised around US$30M, but they aim to break-even in 2010 or 2011. They will still require another round of investment, but hopefully a small one.
Crocus are also working on STT-RAM. Jean-Pierre thinks that the best way forward is Perpendicular STT-RAM, which is currently lead by Toshiba. Crocus' MRAM road map looks like this -
But volume production of STT-RAM is still way off, probably "at least 4-5 years" away according to Jean-Pierre.
In the happy days of 2004, MRAM was hyped as the universal memory - being able to replace your SRAM, DRAM, FLASH and H/D - all in one chip. This is great - but not realistic - at least Jean-Pierre does not believe it. It will require some serious technological breakthrough to compete in particular with NAND Flash, and he just can't see it happen anytime soon. Better to focus on 'niche' memory markets that will take full advantage of the specifics of MRAM - infinite endurance and fast write & read cycles, reliability, small die size and low memory requirements. I'm also quite tired of the old MRAM buzz and hype, and hopefully Crocus and other companies are more sober today and this might actually lead to commercial products. Good luck!
Samsung and Hynix have started to work on 30-nano STT-RAM. They hope to have chips out by the end of the year (probably samples only...). It appears that the Korean government is helping to fund the project.
Samsung and Hynix announced the JV in 2008, they hoped to get commercial chips by 2012. Hynix has licensed STT-RAM technology from Grandis in 2008.
