STT-MRAM - Page 19

Hitachi and Tohoku University have developed n STT-RAM that can be written using multi-level cell (MLC) technology. They actually call their technology SPRAM (spin-transfer torque memory).

The idea is to three-dimensionally stack two TMR elements and connect them in series. This creates , four-value memory (2 bits per cell). Hitachi has already produced a prototype of this memory. The biggest advantage of the MLC SPRAM is that it can reduce bit costs in proportion to the number of stacked TMR elements, Hitachi said. For example, when two TMR elements are stacked, bit costs are reduced by about half.

The US Defense Advanced Research Projects Agency (DARPA) has awarded Grandis with a $8.6 million 2nd phase project for STT-RAM chip development. The first phase ($6.0) was received in October 2008.

Phase 2 will focus on test of verification of STT-RAM integrated memory arrays.

Fujitsu Laboratories has developed a new memory cell circuit for STT-MRAM that reverses the typical order of magnetic tunnel junctions (MTJ) to enable a space savings of 60% and achieve a greater degree of integration

The memory cell circuit in spin-torque-transfer MRAM is a circuit that connects the MTJ element with a cell-select transistor, which act as switches that select which MTJ elements to write to or read from. With existing memory cell circuits, when the MTJ element of a spin-torque-transfer MRAM has been written to a high-resistance state ("1"), voltage is lowered through variable resistance - this requires a larger current to write than when an MTJ element it is switched to a low resistance state ("0"), which is not affected by variable resistance. In other words, because the cell-select transistor's current-driving capability is low, writing to a high-resistance state ("1") would require a significant current. As such, even with a low driving-current capability, cell-select transistors need to be relatively large to ensure an adequate write current, which has been a barrier to reducing transistor size.

There are reports that Hitachi might spin-off their STT-MRAM business. Hitachi calls this technology SPRAM, and plans to devise a 16- and 64-Mbit device in 2012, and a 256-Mbit and 1-Gbit chip by 2015.

Yesterday Crocus has announced a new CEO (Dr. Bertrand F. Cambou) and an 8 million euro investment. Last year we spoke with their previous CEO (Jean-Pierre Braun), and now Dr. Bertrand was kind enough to answer a few questions we had.

Q: The original plan was to release products towards the end of 2009. What's the new target date?
End of 2010 for sampling, mid 2011 for revenue.

Q: Can you tell us a bit more about these products?
At first it will be NV-SRAM 1Mbit. Then we will expand to a family 256Kb-4Mb. We will price it at market price.

Q: When we talked to Jean-Pierre, he estimated the applying the technology for STT-RAM (in 45-60nm) will take at least 4-5 years. What's your view on that?
In my view point the current technology has leg, and will be integrated into CMOS logic all the way to 45nm. STT-TAS will take the relay at 32nm and under within 4-5 years.

Q: Where does he see Crocus' products used in the first few years?
Beside NV-SRAM, Crocus technology should be integrated into logic for embedding memory (replacing SRAM & Flash) into MCU. There is also the opportunity to replace the fuse on SRAM based FPGA to offer re-programable FPGA.

Q: Will Crocus require another round of finance, or do you hope that you can break-even soon?
We will look at strategic corporate partners interested by Crocus technology: NRE/ advance payment on Royalties/ low dilution.....

Dr. Bertrand - thanks again for answering our questions... good luck to both you and Crocus!

Crocus announced an 8 million euro investment, and a change of CEO. The new CEO is Dr. Bertrand F. Cambou. His main task is to bring their MRAM products to the market. Crocus aims to complete the production transfer of its 130nm MRAM technology to manufacturing partner Tower Semiconductor soon.

Crocus has originally planned to start production towards the end of 2009.

Osaka's university has a Spintronics research group that is working towards MRAM and STT-RAM using several materials including Graphene. Here's a nice intro video about the group:

Fujitsu Laboratories and the University of Toronto announced that they have jointly developed the world's first high-reliability read-method for use with spin-torque-transfer (STT) MRAM that is insusceptible to erroneous writes.

STT-MRAM circuit embedded in a CMOS chip

The newly developed read-method uses a negative resistance that is intermediate between the MTJ's high resistance and low resistance on a parallel circuit. If the MTJ is in a high-resistance state, this circuit exhibits negative-resistance characteristics. If the MTJ is in a low-resistance state, then it exhibits normal-resistance characteristics. These characteristics allow the resistance value to be read at lower voltages than before, suppressing the tendency of the read operation to reverse the direction of magnetization and avoiding the problem of erroneous write operations.

Fujitsu Laboratories and the University of Toronto plan to continue with R&D related to STT MRAM to strive toward practical implementation, such as lowering write currents and developing process technologies for further miniaturization.

Researchers from Japan's AIST institute have developed a new Tunnel-Magnetoresistance (or TMR) element with a low data writing current and high data stability. This kind of TMR is required for high-capacity MRAM. In fact the team says that this TMR can be used to make perpendicular STT-MRAM with densities of over 10GBit.

With existing TMRs, there's a trade-off between data writing current and data stability. Data loss happens if the free-layer's magnetization is reversed because of thermal agitation, and if you make a thicker free-layer it solves the data-loss issues, but you need more current. The new design solved this issue by using a free layer that is made from a nonmagnetic layer between two ferromagnetic layers. The resistance to thermal agitation is improved - it is five times better, while the current is only increased by 80%.

The team used an in-plane magnetization film for the free layer, which can be used to make a 1-Gbit MRAM. They plan to make the current even lower with a perpendicular magnetization film, which will allow for a 10 Gbit MRAM device.

The Korean Government has decided to fund STT-RAM research for Hynix and Samsung in a $40 million project. The government will pay around half of the sum for the project, which is intended to run till 2014. The project calls for the government to work with Samsung and Hynix together for research and development on STT-MRAM chips. Korea aims to control around 45% of the 30-nano type memory chip market by 2015.

The companies have already opened a new laboratory at Hangyang University's fusion technology center. It is already equipped with a fully operational 300mm magnetic thin film deposition system and other chip-making facilities.