December 2013

2013 is soon over. If you'd like to reflect back, here are the top 10 stories posted on MRAM-Info in the past year, ranked by popularity:

1. Yole Développement sees the PCM and MRAM markets reaching $1.6 billion in 2018 (Feb 20)
2. Qualcomm and IMEC to jointly research MRAM technologies (Jan 30)
3. Samsung is looking for global STT-MRAM research partners (Jun 4)
4. Sony plans 16Gb ReRAM chips in 2015 (Aug 25)
5. New 3D Spintronics chip could pave the way to high density MRAM (Feb 3)
6. France's MARS project details new MRAM developments (Jul 7)
7. 20 chipmakers from Japan and US to co-develop MRAM (Nov 24)
8. Jusung Engineering to supply MRAM equipment to Crocus's Russia fab (Sep 17)
9. Everspin announces a new MRAM chip with Quad SPI interface (Feb 26)
10. Crocus to develop 8-bit cell MRAM technology for the US IARPA (Apr 10)

I wish all our readers a happy Christmas and a happy new 2014!

Integral Solutions International (ISI) announced a new module the WLA-3000 STT-MRAM Wafer Level Analyzer, the Gen3 Pulser. The new module is optimally matched with its proprietary probecard interface to produce programmable pulses as low as 5nS, with in-situ ability to perform ultra-fast measurements on the MTJs after pulsing.

The tester can be equipped with either the single or dual-channel pulse generator modules for improved UPH. The Gen3 Pulser module was redesigned to speed up Pulse related tests by an order of magnitude and features new Error Rate test (it can measure Error Rate of 10^6 in approximately 2 seconds). It is noew possible to characterize error rate as a function of VBias, Pulse Width/Amplitude, Field and other sweep parameters.

Toshiba announced a new computing architecture that uses only STT-MRAM to perform both operations and storage. The idea support computing capability, register file, primary cache and secondary cache all on the same perpendicular STT-MRAM, and Toshiba says it could lead to CPUs that are drastically faster and more efficient.

Toshiba explains that in the new architecture, the results of operations (answers) that correspond to combinations of certain inputs are prepared in advance in the form of a table and stored in the memory. In response to an input, an answer is read out of the memory. This is equivalent to an operation carried out by a CPU. Because the computation answer is read once, it drastically improves processing speed and power consumption.