December 2010

IBM reports some advances in their racetrack memory program, and they are now able to measure the movement and processing of data as a magnetic pattern on a nanowire (which is 1,000 finer than a human hair).

Racetrack memory uses electron spin to move data on nanowires at hundreds of miles per hour... IBM is not commercializing it yet, but racetrack memory has the potential to be very lower-power and high-density.

UCLA has been awarded $5.5 million from DARPA to continue develop STT-MRAM technologies. This is the second grant for this project, which brings the total DARPA grants to $10.5 million. The first stage has been completed a year early than planned - by meeting (and in fact significantly surpassing) speed, energy consumption and stability requirements of their STT-RAM (write times smaller than 5 nanoseconds and write energies lower than 0.25 picojoules per bit).

The first phase focused on material and structure innovations. In the second phase, the team will further improve the energy and stability, and will build prototype chips. Another important part of the second phase will be statistical studies needed to facilitate integration with CMOS to realize a product.

During the International Electron Device Meeting (IEDM) exhibition we got some updates about STT-MRAM research done at IBM, Samsung and Hynix-Grandis (who are researching STT-MRAM together).

IBM is working together with TDK and has presented a new 4-kbit perpendicular STT-MRAM array using tunnel junctions. Samsung has presented an on-axis MRAM with a novel MTJ, which they say open he way towards sub-30nm scaling. Using ferromagnetic electrode and a different MTJ structure design, Samsung think that they can scale this to a sub-20nm level.