December 2004

Tegal Awarded Another Key Patent for Advanced Sputter Source

The invention provides Tegal with a unique new PVD source technology for advanced applications in chip manufacturing. Direct benefits of this invention include the capability of providing highly directional deposition of metal atoms and ions, and the easy utilization of magnetic target materials such as Nickel.

Conventional PVD sources are limited by their reliance on strong magnetic fields. This makes sputtering of magnetic materials problematic and inefficient. Nickel films will be needed for contact metal silicide formation at the 45-nanometer "node" of chip manufacturing, and in many of the "lead-free" final packaging schemes. The ability to sputter Nickel and other magnetic materials efficiently also has many benefits for MRAM, thin film heads and a wide variety of MEMS applications.

Read the full story Posted: Dec 16,2004

Renesas Technology Develops High-Speed, High-Reliability MRAM Technology

Renesas today announced the development of a high-speed, high-reliability MRAM (Magnetoresistive Random Access Memory) technology for SoC (system-on-a-chip) use. Using this technology, Renesas Technology fabricated a prototype 1-Mbit MRAM employing a 130 nm (nanometer) CMOS process.
Investigation showed the prospect of high-speed operation with an operating frequency of 143 MHz or above at a 1.2 V operating voltage, and measurements in a one-trillion-rewrites experiment confirmed that there was no degradation.

Read more here

Read the full story Posted: Dec 14,2004

TSMC, NEC, Toshiba describe novel MRAM cells

TSMC claims to have developed novel MRAM structures based on a 0.18-micron process and a pillar write word line (PWWL) cell. The company proposes to shrink the bit size by a "so-called ExtVia process" while reducing the writing current by a factor of two.

Toshiba and NEC jointly presented a paper on a low-power 6F2 MRAM based on a cross-point cell. The 1-megabit MRAM chip is said to have been manufactured in a 130-nm process and a 0.24 x 0.48-micron2 magnetic tunnel junction technology. The chip is said to have a 250-ns access time and 1.5-volt operations. "To suppress the sneak current, a cell design is proposed for the new (cross-point) cell with a hierarchical bit line architecture".

Read the full story Posted: Dec 13,2004